View MACH230-15JC_2852170.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

publication# 14132 rev. i amendment /0 issue date: may 1995 mach230-10/15/20 high-density ee cmos programmable logic final com'l: -10/15/20 ind: -18/24 distinctive characteristics 84 pins 128 macrocells 10 ns t pd commercial 18 ns t pd industrial 100 mhz f cnt 70 inputs 64 outputs 128 flip-flops; 4 clock choices 8 pal26v16 blocks with buried macrocells pin-compatible with mach130, mach131, mach231, and mach435 general description the mach230 is a member of th e high-performance ee cmos mach 2 device family. this device has ap- proximately twelve times the logic macrocell capability of the popular pal22v10 without loss of speed. the mach230 consists of eight pal blocks intercon- nected by a programmable switch matrix. the switch matrix connects the pal blocks to each other and to all input pins, providing a high degree of connectivity be- tween the fully-connected pal blocks. this allows designs to be placed and routed efficiently. the mach230 has two kinds of macrocell: output and buried. the output macrocell provides registered, latched, or combinatorial outputs with programmable polarity. if a registered configuration is chosen, the reg- ister can be configured as d-type or t-type to help reduce the number of product terms. the register type decision can be made by the designer or by the soft- ware. all output macrocells can be connected to an i/o cell. if a buried macrocell is desired, the internal feed- back path from the macrocell can be used, which frees up the i/o pin for use as an input. the mach230 has dedicated buried macrocells which, in addition to the capabilities of the output macrocell, also provide input registers for use in synchronizing signals and reducing setup time requirements. block diagram if you would like to view block diagram in full size, please click on the box. lattice semiconductor
52 x 68 and logic array and logic allocator 52 x 68 and logic array and logic allocator 52 x 68 and logic array and logic allocator 52 x 68 and logic array and logic allocator 52 x 68 and logic array and logic allocator 52 x 68 and logic array and logic allocator 26 26 26 i/o 56 - i/o 63 (block h) i/o 48 - i/o 55 (block g) i/o 40 - i/o 47 (block f) i/o 31 - i/o 39 (block e) i/o 24 - i/o 31 (block d) i/o 8 - i/o 15 (block b) i/o cells macrocells 8 macrocells 8 8 i/o cells macrocells 8 macrocells 8 8 i/o cells macrocells 8 macrocells 8 8 52 x 68 and logic array and logic allocator clk 0 /i 0, clk 1 /i 1 clk 2 /i 3, clk 3 /i 4 i 2, i 5 14132i1 i/o 0 - i/o 7 (block a) macrocells macrocells 8 8 8 i/o cells macrocells macrocells 8 8 8 i/o cells macrocells macrocells 8 8 8 i/o cells i/o cells macrocells 8 macrocells 8 8 switch matrix macrocells macrocells 8 8 8 i/o cells 8 8 8 8 4 2 8 8 8 4 4 8 i/o 16 - i/o 23 (block c) 26 26 26 26 26 52 x 68 and logic array and logic allocator oe oe oe oe oe oe oe oe siblings siblings siblings siblings
3 mach230-10/15/20 connection diagram top view pin designations clk/i = clock or input gnd = ground i = input i/o = input/output v cc = supply voltage note: pin-compatible with mach130, mach131, mach231, and mach435. 84 plcc 14132i-2 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 clk 0 /i 0 v cc gnd clk 1 /i 1 i/o 16 i/o 17 i/o 18 i/o 19 i/o 20 i/o 21 i/o 22 i/o 23 gnd gnd i/0 6 i/o 5 i/o 4 i/o 3 i/o 1 i/o 0 v cc gnd v cc i 5 i/o 63 i/o 62 i/o 61 i/o 60 i/o 59 i/o 58 i/o 57 i/o 2 gnd i/o 55 i/o 54 i/o 53 i/o 52 i/o 51 i/o 50 i/o 49 i/o 48 clk 3 /i 4 gnd v cc clk 2 /i 3 i/o 47 i/o 46 i/o 45 i/o 44 i/o 43 i/o 42 i/o 41 i/o 40 i/o 24 i/o 25 i/o 26 i/o 27 i/o 28 i/o 29 i/o 30 i/o 31 i 2 v cc gnd v cc i/o 32 i/o 33 i/o 34 i/o 35 i/o 36 i/o 37 i/o 38 i/o 39 gnd i/o 7 111098765432184838281807978777675 31 32 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 33 i/o 56 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 54 55 12 13
4 mach230-10/15/20 (com'l) ordering information commercial products p rogrammable logic products for commercial applications are available with several ordering options. the order number (valid combination) is formed by a combination of: operating conditions c = commercial (0 c to +70 c) family type mach = macro array cmos high-speed speed -10 = 1 0 ns t pd -15 = 15 ns t pd -20 = 20 ns t pd mach230-10 mach230-15 mach230-20 mach -10 j c valid combinations the valid combinations table lists configurations planned to be supported in volume for this device. con- sult yo ur local sales office to confirm availability of specific valid combinations and to check on newly re- leased combinations. valid combinations optional processing blank = standard processing 230 device number 230 = 128 macrocells, 84 pins package type j = 84-pin plastic leaded chip carrier (pl 084) jc
5 mach230-18/24 (ind) ordering information industrial products p rogrammable logic products for industrial applications are available with several ordering options. the order number (valid combination) is formed by a combination of: operating conditions i = industrial (C40 c to +85 c) family type mach = macro array cmos high-speed speed -18 = 1 8 ns t pd -24 = 24 ns t pd mach230-18 mach230-24 mach -18 j i valid combinations the valid combinations table lists configurations planned to be supported in volume for this device. consul t yo u r local sales office to confirm availabil- ity of specific valid combinations and to check on newly released combinations. valid combinations optional processing blank = standard processing 230 device number 230 = 128 macrocells, 84 pins package type j = 84-pin plastic leaded chip carrier (pl 084) ji
6 mach230-10/15/20 functional description the mach230 consists of eight pal blocks connected by a switch matrix. there are 64 i/o pins and 2 dedicated input pins feeding the switch matrix. these signals are distributed to the four pal blocks for efficient design implementation. there are 4 clock pins that can also be used as dedicated inputs. the pal blocks each pal block in the mach230 (figure 1) contains a 64-product-term logic array, a logic allocator, 8 output macrocells, 8 buried macrocells, and 8 i/o cells. the switch matrix feeds each pal block with 26 inputs. this makes the pal block look effectively like an independ- ent pal26v16 with 8 buried macrocells. in addition to the logic product terms, two output enable product terms, an asynchronous reset product term, and an asynchronous preset product term are provided. one of the two output enable product terms can be chosen within each i/o cell in the pal block. all flip-flops within the pal block are initialized together. the switch matrix the mach230 switch matrix is fed by the inputs and feedback signals from the pal blocks. each pal block provides 16 internal feedback signals and 8 i/o feedback signals. the switch matrix distributes these signals back to the pal blocks in an efficient manner that also provides for high performance. the design software automatically configures the switch matrix when fitting a design into the device. the mach230 places a restriction on buried macrocell feedback only. buried macrocell feedback from one block can be used as an input only to that block or its sibling block. sibling blocks are illustrated in the block diagram and in table 1. output macrocell feedback is not restricted. table 1. sibling blocks pal block sibling block ah bg cf de ed fc gb ha the product-term array the mach230 product-term array consists of 64 product terms for logic use, and 4 special-purpose product terms. two of the special-purpose product terms provide programmable output enable, one provides asynchronous reset, and one provides asyn- chronous preset. the logic allocator the logic allocator in the mach230 takes the 64 logic product terms and allocates them to the 16 macrocells as needed. each macrocell can be driven by up to 16 product terms. the design software automatically configures the logic allocator when fitting the design into the device. table 2 illustrates which product term clusters are available to each macrocell within a pal block. refer to figure 1 for cluster and macrocell numbers. table 2. logic allocation available output buried clusters m 0 c 0 , c 1 , c 2 m 1 c 0 , c 1 , c 2 , c 3 m 2 c 1 , c 2 , c 3 , c 4 m 3 c 2 , c 3 , c 4 , c 5 m 4 c 3 , c 4 , c 5 , c 6 m 5 c 4 , c 5 , c 6 , c 7 m 6 c 5 , c 6 , c 7 , c 8 m 7 c 6 , c 7 , c 8 , c 9 m 8 c 7 , c 8 , c 9 , c 10 m 9 c 8 , c 9 , c 10 , c 11 m 10 c 9 , c 10 , c 11 , c 12 m 11 c 10 , c 11 , c 12 , c 13 m 12 c 11 , c 12 , c 13 , c 14 m 13 c 12 , c 13 , c 14 , c 15 m 14 c 13 , c 14 , c 15 m 15 c 14 , c 15 macrocell the macrocell the mach230 has two types of macrocell: output and buried. the output macrocells can be configured as either registered, latched, or combinatorial, with pro- grammable polarity. the macrocell provides internal feedback whether configured with or without the flip- flop. the registers can be configured as d-type or t-type, allowing for product-term optimization. the flip-flops can individually select one of four clock/ gate pins, which are also available as data inputs. the registers are clocked on the low-to-high transition of the clock signal. the latch holds its data when the gate input is high, and is transparent when the gate input is low. the flip-flops can also be asynchronously initial- ized with the common asynchronous reset and preset product terms. the buried macrocells are the same as the output macrocells if they are used for generating logic. in that case, the only thing that distinguishes them from the output macrocells is the fact that there is no i/o cell connection, and the signal is only used internally. the buried macrocell can also be configured as an input register or latch. the i/o cell the i/o cell in the mach230 consists of a three-state output buffer. the three-state buffer can be configured in one of three ways: always enabled, always disabled, or controlled by a product term. if product term control is chosen, one of two product terms may be used to provide the control. the two product terms that are available are common to all i/o cells in a pal block. these choices make it possible to use the macrocell as an output, an input, a bidirectional pin, or a three-state output for use in driving a bus.
7 mach230-10/15/20 0 4 8 12 16 20 24 28 4032 43 36 0 4 8 12 16 20 24 28 4032 43 36 i/o cell i/o i/o i/o i/o i/o i/o i/o i/o switch matrix output enable output enable asynchronous reset asynchronous preset 16 i/o cell i/o cell i/o cell i/o cell i/o cell i/o cell i/o cell output macro cell output macro cell output macro cell output macro cell output macro cell output macro cell output macro cell output macro cell 8 buried macro cell buried macro cell buried macro cell buried macro cell buried macro cell buried macro cell buried macro cell buried macro cell 47 51 47 51 clk 4 0 logic allocator 63 c 0 c 1 c 2 c 3 c 4 c 5 c 6 c 7 c 8 c 9 c 10 c 11 c 12 c 13 c 14 c 15 m 3 m 6 m 5 m 4 m 2 m 1 m 0 m 9 m 8 m 7 m 10 m 11 m 12 m 13 m 14 m 15 14132i-3 figure 1. mach230 pal block
mach230-10 (com'l)8 absolute maximum ratings storage temperature C65 c to +150 c . . . . . . . . . . . ambient temperature with power applied C55 c to +125 c . . . . . . . . . . . . . supply voltage with respect to ground C0.5 v to +7.0 v . . . . . . . . . . . . . dc input voltage C0.5 v to v cc + 0.5 v . . . . . . . . . . . . dc output or i/o pin voltage C0.5 v to v cc + 0.5 v . . . . . . . . . . . . . . . . static discharge voltage 2001 v . . . . . . . . . . . . . . . . latchup current (t a = 0 c to 70 c) 200 ma . . . . . . . . . . . . . . . . . . . . . stresses above those listed under absolute maximum ratings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. pro- gramming conditions may differ. operating ranges commercial (c) devices ambient temperature (t a ) operating in free air 0 c to +70 c . . . . . . . . . . . . . . supply voltage (v cc ) with respect to ground +4.75 v to +5.25 v . . . . . . . . operating ranges define those limits between which the func- tionality of the device is guaranteed. dc characteristics over commercial operating ranges unless otherwise specified parameter symbol parameter description test conditions min typ max unit v oh output high voltage i oh = C3.2 ma, v cc = min 2.4 v v in = v ih or v il v ol output low voltage i ol = 16 ma, v cc = min 0.5 v v in = v ih or v il v ih input high voltage guaranteed input logical high 2.0 v voltage for all inputs (note 1) v il input low voltage guaranteed input logical low 0.8 v voltage for all inputs (note 1) i ih input high current v in = 5.25 v, v cc = max (note 2) 10 m a i il input low current v in = 0 v, v cc = max (note 2) C10 m a i ozh off-state output leakage v out = 5.25 v, v cc = max 10 m a current high v in = v ih or v il (note 2) i ozl off-state output leakage v out = 0 v, v cc = max C10 m a current low v in = v ih or v il (note 2) i sc output short-circuit current v out = 0.5 v, v cc = max (note 3) C30 C130 ma i cc supply current v in = 0 v, outputs open (i out = 0 ma) 235 ma v cc = 5.0 v, f = 25 mhz, t a = 25 c (note 4) notes: 1. these are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. i/o pin leakage is the worst case of i il and i ozl (or i ih and i ozh ). 3. not more than one output should be shorted at a time. duration of the short-circuit should not exceed one second. v out = 0.5 v has been chosen to avoid test problems caused by tester ground degradation. 4. this parameter is measured with a 16-bit up/down counter pattern. this pattern is programmed in each pal block and capable of being loaded, enabled, and reset.
mach230-10 (com'l) 9 capacitance (note 1) parameter symbol parameter description test conditions typ unit c in input capacitance v in = 2.0 v v cc = 5.0 v, t a = 25 c6pf c out output capacitance v out = 2.0 v f = 1 mhz 8 p f switching characteristics over commercial operating ranges parameter symbol parameter description min max unit t pd input, i/o, or feedback to combinatorial output 10 ns d-type 6.5 ns t-type 7.5 ns t h register data hold time 0 n s t co clock to output 6.5 ns t wl clock low 4 n s t wh width high 4 n s d-type 77 mhz t-type 72 mhz f max d-type 100 mhz t-type 91 mhz 125 mhz t sl setup time from input, i/o, or feedback to gate 8 n s t hl latch data hold time 0 n s t go gate to output 7.5 ns t gwl gate width low 4 n s t pdl input, i/o, or feedback to output through transparent 14 ns input or output latch t sir input register setup time 2 n s t hir input register hold time 2.5 ns t ico input register clock to combinatorial output 15.5 ns t ics input register clock to output register setup d-type 11 ns t-type 12 ns t wicl input register low 4 n s t wich clock width high 4 n s f maxir maximum input register frequency 125 mhz t sil input latch setup time 2 n s t hil input latch hold time 2.5 ns t igo input latch gate to combinatorial output 17 ns t igol input latch gate to output through transparent 18 ns output latch t sll setup time from input, i/o, or feedback through 10 ns transparent input latch to output latch gate -10 maximum frequency t s setup time from input, i/o, or feedback to clock external feedback internal feedback (f cnt ) no feedback
mach230-10 (com'l)10 switching characteristics over commercial operating ranges (continued) parameter symbol parameter description min max unit t igs input latch gate to output latch setup 11 ns t wigl input latch gate width low 4 n s t pdll input, i/o, or feedback to output through transparent 16 ns input and output latches t ar asynchronous reset to registered or latched output 18 ns t arw asynchronous reset width 10 ns t arr asynchronous reset recovery time 10 ns t ap asynchronous preset to registered or latched output 18 ns t apw asynchronous preset width 10 ns t apr asynchronous preset recovery time 10 ns t ea input, i/o, or feedback to output enable 15 ns t er input, i/o, or feedback to output disable 15 ns -10 note: 1. these parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected.
mach230-15/20 (com'l) 11 absolute maximum ratings storage temperature C65 c to +150 c . . . . . . . . . . . ambient temperature with power applied C55 c to +125 c . . . . . . . . . . . . . supply voltage with respect to ground C0.5 v to +7.0 v . . . . . . . . . . . . . dc input voltage C0.5 v to v cc + 0.5 v . . . . . . . . . . . . dc output or i/o pin voltage C0.5 v to v cc + 0.5 v . . . . . . . . . . . . . . . . static discharge voltage 2001 v . . . . . . . . . . . . . . . . latchup current (t a = 0 c to 70 c) 200 ma . . . . . . . . . . . . . . . . . . . . . stresses above those listed under absolute maximum ratings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. pro- gramming conditions may differ. operating ranges commercial (c) devices ambient temperature (t a ) operating in free air 0 c to +70 c . . . . . . . . . . . . . . supply voltage (v cc ) with respect to ground +4.75 v to +5.25 v . . . . . . . . operating ranges define those limits between which the func- tionality of the device is guaranteed. dc characteristics over commercial operating ranges unless otherwise specified parameter symbol parameter description test conditions min typ max unit v oh output high voltage i oh = C3.2 ma, v cc = min 2.4 v v in = v ih or v il v ol output low voltage i ol = 16 ma, v cc = min 0.5 v v in = v ih or v il v ih input high voltage guaranteed input logical high 2.0 v voltage for all inputs (note 1) v il input low voltage guaranteed input logical low 0.8 v voltage for all inputs (note 1) i ih input high current v in = 5.25 v, v cc = max (note 2) 10 m a i il input low current v in = 0 v, v cc = max (note 2) C10 m a i ozh off-state output leakage v out = 5.25 v, v cc = max 10 m a current high v in = v ih or v il (note 2) i ozl off-state output leakage v out = 0 v, v cc = max C10 m a current low v in = v ih or v il (note 2) i sc output short-circuit current v out = 0.5 v, v cc = max (note 3) C30 C130 ma i cc supply current (typical) v cc = 5 v, t a = 25 c, f = 25 mhz 235 ma (note 4) notes: 1. these are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. i/o pin leakage is the worst case of i il and i ozl (or i ih and i ozh ). 3. not more than one output should be shorted at a time. duration of the short-circuit should not exceed one second. v out = 0.5 v has been chosen to avoid test problems caused by tester ground degradation. 4. measured with a 16-bit up/down counter pattern. this pattern is programmed in each pal block and is capable of being loaded, enabled, and reset.
mach230-15/20 (com'l)12 capacitance (note 1) parameter symbol parameter description test conditions typ unit c in input capacitance v in = 2.0 v v cc = 5.0 v, t a = 25 c6pf c out output capacitance v out = 2.0 v f = 1 mhz 8 p f switching characteristics over commercial operating ranges (note 2) parameter symbol parameter description min max min max unit t pd input, i/o, or feedback to combinatorial output (note 3) 15 20 ns d-type 10 13 ns t-type 11 14 ns t h register data hold time 0 0 ns t co clock to output (note 3) 10 12 ns t wl clock low 6 8 ns t wh width high 6 8 ns d-type 50 40 mhz t-type 47.6 38.5 mhz f max d-type 66.6 50 mhz t-type 62.5 47.6 mhz 83.3 62.5 mhz t sl setup time from input, i/o, or feedback to gate 10 13 ns t hl latch data hold time 0 0 ns t go gate to output (note 3) 11 12 ns t gwl gate width low 6 8 ns t pdl input, i/o, or feedback to output through transparent input or output latch 17 22 ns t sir input register setup time 2 2 ns t hir input register hold time 2.5 3 n s t ico input register clock to combinatorial output 18 23 ns t ics input register clock to output register setup d-type 15 20 ns t-type 16 21 ns t wicl input register low 6 8 ns t wich clock width high 6 8 ns f maxir maximum input register frequency 1/(t wicl + t wich ) 83.3 62.5 mhz t sil input latch setup time 2 2 ns t hil input latch hold time 2.5 3 n s t igo input latch gate to combinatorial output 20 25 ns t igol input latch gate to output through transparent output latch 22 27 ns t sll setup time from input, i/o, or feedback through transparent input latch to output latch gate 12 15 ns t igs input latch gate to output latch setup 16 21 ns -15 -20 maximum frequency (note 1) t s setup time from input, i/o, or feedback to clock external feedback internal feedback (f cnt ) no feedback 1/(t wl + t wh ) 1/(t s + t co )
mach230-15/20 (com'l) 13 switching characteristics over commercial operating ranges (note 2) (continued) parameter symbol parameter description min max min max unit t wigl input latch gate width low 6 8 ns t pdll input, i/o, or feedback to output through transparent 19 24 ns input and output latches t ar asynchronous reset to registered or latched output 20 25 ns t arw asynchronous reset width (note 1) 15 20 ns t arr asynchronous reset recovery time (note 1) 10 15 ns t ap asynchronous preset to registered or latched output 20 25 ns t apw asynchronous preset width (note 1) 15 20 ns t apr asynchronous preset recovery time (note 1) 10 15 ns t ea input, i/o, or feedback to output enable (note 3) 15 20 ns t er input, i/o, or feedback to output disable (note 3) 15 20 ns notes: 1. these parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where frequency may be affected. 2. see switching test circuit for test conditions. 3. parameters measured with 32 outputs switching. -15 -20
14 mach230-18/24 (ind) absolute maximum ratings storage temperature C65 c to +150 c . . . . . . . . . . . ambient temperature with power applied C55 c to +125 c . . . . . . . . . . . . . supply voltage with respect to ground C0.5 v to +7.0 v . . . . . . . . . . . . . dc input voltage C0.5 v to v cc + 0.5 v . . . . . . . . . . . . dc output or i/o pin voltage C0.5 v to v cc + 0.5 v . . . . . . . . . . . . . static discharge voltage 2001 v . . . . . . . . . . . . . . . . . latchup current (t a =C40 c to +85 c) 200 ma . . . . . . . . . . . . . . . . . . stresses above those listed under absolute maximum ratings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. programming conditions may differ. industrial operating ranges ambient temperature (t a ) operating in free air C40 c to +85 c . . . . . . . . . . . . supply voltage (v cc ) with respect to ground +4.5 v to +5.5 v. . . . . . . . . . . . . . operating ranges define those limits between which the func- tionality of the device is guaranteed. dc characteristics over industrial operating ranges unless otherwise specified parameter symbol parameter description test conditions min typ max unit v oh output high voltage i oh = C3.2 ma, v cc = min 2.4 v v in = v ih or v il v ol output low voltage i ol = 16 ma, v cc = min 0.5 v v in = v ih or v il v ih input high voltage guaranteed input logical high 2.0 v voltage for all inputs (note 1) v il input low voltage guaranteed input logical low 0.8 v voltage for all inputs (note 1) i ih input high leakage current v in = 5.25 v, v cc = max (note 2) 10 m a i il input low leakage current v in = 0 v, v cc = max (note 2) C10 m a i ozh off-state output leakage v out = 5.25 v, v cc = max 10 m a current high v in = v ih or v il (note 2) i ozl off-state output leakage v out = 0 v, v cc = max C10 m a current low v in = v ih or v il (note 2) i sc output short-circuit current v out = 0.5 v, v cc = max (note 3) C30 C130 ma i cc supply current (typical) v cc = 5 v, t a = 25 c, f = 25 mhz (note 4) 235 ma notes: 1. these are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. i/o pin leakage is the worst case of i il and i ozl (or i ih and i ozh ). 3. not more than one output should be shorted at a time. duration of the short-circuit should not exceed one second. v out = 0.5 v has been chosen to avoid test problems caused by tester ground degradation. 4. measured with a 16-bit up/down counter pattern. this pattern is programmed in each pal block and is capable of being loaded, enabled, and reset.
15 mach230-18/24 (ind) capacitance (note 1) parameter symbol parameter description test conditions typ unit c in input capacitance v in = 2.0 v v cc = 5.0 v, t a = 25 c6pf c out output capacitance v out = 2.0 v f = 1 mhz 8 p f switching characteristics over industrial operating ranges (note 2) parameter symbol parameter description min max min max unit t pd input, i/o, or feedback to combinatorial output (note 3) 18 24 ns d-type 12 16 ns t-type 13.5 17 ns t h register data hold time 0 0 ns t co clock to output (note 3) 12 14.5 ns t wl clock low 7.5 10 ns t wh width high 7.5 10 ns d-type 40 32 mhz t-type 38 30.5 mhz f max d-type 53 38 mhz t-type 44 34.5 mhz 66.5 50 mhz t sl setup time from input, i/o, or feedback to gate 12 16 ns t hl latch data hold time 0 0 ns t go gate to output (note 3) 13.5 14.5 ns t gwl gate width low 7.5 10 ns t pdl input, i/o, or feedback to output through transparent 20.5 26.5 ns input or output latch t sir input register setup time 2.5 2.5 ns t hir input register hold time 3.5 4 n s t ico input register clock to combinatorial output 22 28 ns t ics input register clock to output register setup d-type 18 24 ns t-type 19.5 25.5 ns t wicl input register low 7.5 10 ns t wich clock width high 7.5 10 ns f maxir maximum input register frequency 1/(t wicl + t wich ) 66.5 50 mhz t sil input latch setup time 2.5 2.5 ns t hil input latch hold time 3.5 4 n s t igo input latch gate to combinatorial output 24 30 ns t igol input latch gate to output through transparent 26.5 32.5 ns output latch t sll setup time from input, i/o, or feedback through 14.5 18 ns transparent input latch to output latch gate t igs input latch gate to output latch setup 19.5 25.5 ns t wigl input latch gate width low 7.5 10 ns t pdll input, i/o, or feedback to output through transparent 23 29 ns input and output latches -18 -24 maximum frequency (note 1) t s setup time from input, i/o, or feedback to clock external feedback internal feedback (f cnt ) no feedback 1/(t wl + t wh ) 1/(t s + t co )
16 mach230-18/24 (ind) switching characteristics over industrial operating ranges (note 2) (continued) parameter symbol parameter description min max min max unit t ar asynchronous reset to registered or latched output 24 30 ns t arw asynchronous reset width (note 1) 18 24 ns t arr asynchronous reset recovery time (note 1) 12 18 ns t ap asynchronous preset to registered or latched output 24 30 ns t apw asynchronous preset width (note 1) 18 24 ns t apr asynchronous preset recovery time (note 1) 12 18 ns t ea input, i/o, or feedback to output enable (note 3) 18 24 ns t er input, i/o, or feedback to output disable (note 3) 18 24 ns notes: 1. these parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where frequency may be affected. 2. see switching test circuit for test conditions. 3. parameters measured with 32 outputs switching. -18 -24
17 mach230-10/15/20 typical current vs. voltage (i-v) characteristics v cc = 5.0 v, t a = 25 c input 20 C40 C60 C80 C2 C1 123 output, high i i (ma) v i (v) C20 i oh (ma) v oh (v) 25 C50 C75 C100 C3 C2 C1 123 C25 C125 C150 45 45 C100 C0.8 C0.6 C0.4 .2 C0.2C1.0 output, low .4 .6 1.0 .8 60 40 20 C20 C40 80 C60 C80 i ol (ma) v ol (v) 14132i-4 14132i-5 14132i-6
18 mach230-10/15/20 typical i cc characteristics v cc = 5 v, t a = 25 c 300 275 250 225 200 175 150 125 100 75 50 25 0 0 10 20 3040 50 6070 mach230 i cc (ma) frequency (mhz) 14132i-7 the selected typical pattern is a 16-bit up/down counter. this pattern is programmed in each pal block and is capable of being loaded, enabled, and reset. maximum frequency shown uses internal feedback and a d-type register.
19 mach230-10/15/20 typical thermal characteristics measured at 25 c ambient. these parameters are not tested. parameter symbol parameter description plcc units q jc thermal impedance, junction to case 5 c/w q ja thermal impedance, junction to ambient 20 c/w q jma thermal impedance, junction to 200 lfpm air 17 c/w 400 lfpm air 14 c/w 600 lfpm air 12 c/w 800 lfpm air 10 c/w plastic q jc considerations the data listed for plastic q jc are for reference only and are not recommended for use in calculating junction temperatures. the heat-flow paths in plastic-encapsulated devices are complex, making the q jc measurement relative to a specific location on the package surface. tests indicate this measurement reference point is directly below the die-attach area on the bottom center of the package. furthermore, q jc tests on packages are performed in a constant-temperature bath, keeping the package surface at a constant temperature. therefore, the measurements can only be used in a similar environment. typ ambient with air flow
20 mach230-10/15/20 switching waveforms notes: 1. v t = 1.5 v. 2. input pulse amplitude 0 v to 3.0 v. 3. input rise and fall times 2 nsC4 ns typical. t pd input, i/o, or feedback combinatorial output v t v t combinatorial output v t input, i/o, or feed- back registered output registered output t s t co v t t h v t clock t wh clock clock width t wl v t combinatorial output registered input (mach 2 and 4) t sir t ico v t t hir v t input register clock registered input latched output (mach 2, 3, and 4) gate gate width (mach 2, 3, and 4) t gws v t v t v t v t t ics input register to output register setup (mach 2 and 4) output register clock input register clock registered input t pdl input, i/o, or feedback latched out gate v t t hl t sl t go v t v t 14132i-8 14132i-9 14132i-10 14132i-11 14132i-12 14132i-13 14132i-14
21 mach230-10/15/20 switching waveforms notes: 1. v t = 1.5 v. 2. input pulse amplitude 0 v to 3.0 v. 3. input rise and fall times 2 nsC4 ns typical. latched input (mach 2 and 4) latched input and output (mach 2, 3, and 4) latched in output latch gate latched out t sll combinatorial output gate t hil t sil t igo latched in t pdll t igol t igs input latch gate v t v t v t v t v t v t 14132i-15 14132i-16
22 mach230-10/15/20 switching waveforms t wich clock input register clock width (mach 2 and 4) v t t wicl v t v t t arw v t t ar asynchronous reset input, i/o, or feedback registered output clock t arr asynchronous preset registered output clock v t v t outputs output disable/enable t er t ea v oh - 0.5v v ol + 0.5v notes: 1. v t = 1.5 v. 2. input pulse amplitude 0 v to 3.0 v. 3. input rise and fall times 2 nsC4 ns typical. input, i/o, or feedback v t v t input, i/o, or feedback t apw v t t ap t apr input latch gate input latch gate width (mach 2 and 4) t wigl v t 14132i-17 14132i-18 14132i-19 14132i-20 14132i-21
23 mach230-10/15/20 key to switching waveforms ks000010-pal must be steady may change from h to l may change from l to h does not apply don't care, any change permitted will be steady will be changing from h to l will be changing from l to h changing, state unknown center line is high- impedance off state waveform inputs outputs switching test circuit measured specification s 1 c l r 1 r 2 output value t pd , t co closed 1.5 v t ea z ? h: open 35 pf 1.5 v z ? l: closed 300 w 390 w t er h ? z: open 5 pf h ? z: v oh C 0.5 v l ? z: closed l ? z: v ol + 0.5 v commercial 14132i-22 c l output r 1 r 2 s 1 test point 5 v *switching several outputs simultaneously should be avoided for accurate measurement.
24 mach230-10/15/20 f max parameters the parameter f max is the maximum clock rate at which the device is guaranteed to operate. because the flexi- bility inherent in programmable logic devices offers a choice of clocked flip-flop designs, f max is specified for three types of synchronous designs. the first type of design is a state machine with feedback signals sent off-chip. this external feedback could go back to the device inputs, or to a second device in a multi-chip state machine. the slowest path defining the period is the sum of the clock-to-output time and the in- put setup time for the external signals (t s + t co ). the re- ciprocal, f max , is the maximum frequency with external feedback or in conjunction with an equivalent speed de- vice. this f max is designated f max external. the second type of design is a single-chip state ma- chine with internal feedback only. in this case, flip-flop inputs are defined by the device inputs and flip-flop out- puts. under these conditions, the period is limited by the internal delay from the flip-flop outputs through the inter- nal feedback and logic to the flip-flop inputs. this f max is designated f max internal. a simple internal counter is a good example of this type of design; therefore, this pa- rameter is sometimes called f cnt. the third type of design is a simple data path applica- tion. in this case, input data is presented to the flip-flop and clocked through; no feedback is employed. under these conditions, the period is limited by the sum of the data setup time and the data hold time (t s + t h ). however, a lower limit for the period of each f max type is the mini- mum clock period (t wh + t wl ). usually, this minimum clock period determines the period for the third f max , des- ignated f max no feedback. for devices with input registers, one additional f max pa- rameter is specified: f maxir . because this involves no feedback, it is calculated the same way as f max no feed- back. the minimum period will be limited either by the sum of the setup and hold times (t sir + t hir ) or the sum of the clock widths (t wicl + t wich ). the clock widths are nor- mally the limiting parameters, so that f maxir is specified as 1/(t wicl + t wich ). note that if both input and output reg- isters are use in the same path, the overall frequency will be limited by t ics . all frequencies except f max internal are calculated from other measured ac parameters. f max internal is meas- ured directly. t hir t sir logic register tt clk (second chip) sco t s f max external; 1/(t s + t co ) logic register clk f max internal (f cnt ) logic register t clk s f max no feedback; 1/(t s + t h ) or 1/(t wh + t wl ) 14132i-23 logic register clk f maxir ; 1/(t sir + t hir ) or 1/(t wicl + t wich )
25 mach230-10/15/20 endurance characteristics the mach families are manufactured using our advanced electrically erasable process. this technol- ogy uses an ee cell to replace the fuse link used in bipolar parts. as a result, the device can be erased and reprogrammed, a feature which allows 100% testing at the factory. endurance characteristics parameter symbol parameter description min units test conditions 10 years max storage temperature 20 years max operating temperature n max reprogramming cycles 100 cycles normal programming conditions t dr min pattern data retention time
26 mach230-10/15/20 input/output equivalent schematics input i/o preload circuitry esd protection feedback input v cc v cc 1 k w 100 k w v cc v cc 100 k w 1 k w 14132i-24
27 mach230-10/15/20 power-up reset the mach devices have been designed with the capa- bility to reset during system power-up. following power- up, all flip-flops will be reset to low. the output state will depend on the logic polarity. this feature provides extra flexibility to the designer and is especially valuable in simplifying state machine initialization. a timing dia- gram and parameter table are shown below. due to the synchronous operation of the power-up reset and the wide range of ways v cc can rise to its steady state, two conditions are required to insure a valid power-up reset. these conditions are: 1. the v cc rise must be monotonic. 2. following reset, the clock input must not be driven from low to high until all applicable input and feedback setup times are met. parameter symbol parameter descriptions max unit t pr power-up reset time 10 m s t s input or feedback setup time t wl clock width low see switching characteristics t pr t wl t s 4 v v cc power registered output clock 14132i-25 power-up reset waveform
28 mach230-10/15/20 using preload and observability in order to be testable, a circuit must be both controllable and observable. to achieve this, the mach devices incorporate register preload and observability. in preload mode, each flip-flop in the mach device can be loaded from the i/o pins, in order to perform functional testing of complex state machines. register preload makes it possible to run a series of tests from a known starting state, or to load illegal states and test for proper recovery. this ability to control the mach device's internal state can shorten test sequences, since it is easier to reach the state of interest. the observability function makes it possible to see the internal state of the buried registers during test by overriding each register's output enable and activating the output buffer. the values stored in output and buried registers can then be observed on the i/o pins. without this feature, a thorough functional test would be impossible for any designs with buried registers. while the implementation of the testability features is fairly straightforward, care must be taken in certain instances to insure valid testing. one case involves asynchronous reset and preset. if the mach registers drive asynchronous reset or preset lines and are preloaded in such a way that reset or preset are asserted, the reset or preset may remove the preloaded data. this is illustrated in figure 2. care should be taken when planning functional tests, so that states that will cause unexpected resets and presets are not preloaded. another case to be aware of arises in testing combinato- rial logic. when an output is configured as combinato- rial, the observability feature forces the output into registered mode. when this happens, all product terms are forced to zero, which eliminates all combinatorial data. for a straight combinatorial output, the correct value will be restored after the preload or observe function, and there will be no problem. if the function implements a combinatorial latch, however, it relies on feedback to hold the correct value, as shown in fugure 3. as this value may change during the preload or observe operation, you cannot count on the data being correct after the operation. to insure valid testing in these cases, outputs that are combinatorial latches should not be tested immediately following a preload or observe sequence, but should first be restored to a known state. all mach 2 devices support both preload and observability. contact individual programming vendors in order to verify programmer support. ar figure 2. preload/reset conflict q 1 on off preload mode q 2 ar preloaded high d q q 1 d q ar preloaded high q 2 14132i-26 figure 3. combinatorial latch set reset 14132i-27
33 mach230-10/15/20 physical dimensions* pl 084 84-pin plastic leaded chip carrier (measured in inches) top view seating plane 1.185 1.195 1.150 1.156 pin 1 i.d. .026 .032 .050 ref .042 .056 .062 .083 .013 .021 1.000 ref .007 .013 .165 .180 .090 .130 16-038-sq pl 084 df79 8-1-95 ae side view 1.185 1.195 1.150 1.156 1.090 1.130 *for reference only. bsc is an ansi standard for basic space centering.

▲Up To Search▲

Price & Availability of MACH230-15JC

	To Download MACH230-15JC Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .